In capacitively coupled plasma (CCP) chambers, integrated circuits are formed from a wafer or substrate over which are formed patterned microelectronics layers. In the processing of the substrate, plasma is generated between upper and lower electrodes and often employed to deposit films on the substrate or to etch intended portions of the films. The chambers exhibit etch rate drop and etch uniformity drift after a large number of radio frequency (RF) hours are run using the electrodes. The decline of etch performance results from changes in the morphology of the silicon surface of the electrodes as well as contamination of plasma exposed surfaces of the electrodes. Thus, there is a need for a systematic and effective methodology to clean the electrodes and reduce surface roughness so that the electrodes meet surface contamination specifications and manufacturing yields are enhanced.